SrTiO₃ on Silicon and SOI Wafers for Quantum and Cryogenic Devices
La Luce Cristallina manufactures epitaxial strontium titanate (SrTiO₃/STO) wafer platforms integrated with silicon (Si) and silicon-on-insulator (SOI) for advanced quantum, cryogenic, nonlinear, and semiconductor device applications.
At cryogenic temperatures, SrTiO₃ exhibits quantum paraelectric behavior and a voltage-tunable dielectric response, providing unique material properties for researchers and device developers exploring next-generation quantum and low-temperature technologies.
SrTiO₃ for Advanced Device Applications
La Luce Cristallina brings high-quality epitaxial SrTiO₃ to silicon-compatible wafer platforms, providing researchers with a foundation for integrating the unique functional properties of crystalline STO into advanced devices.
Our SrTiO₃ platforms support research and development in areas where tunable dielectric behavior, cryogenic operation, and crystalline oxide integration can enable new device architectures.
Available SrTiO₃ Wafer Platforms
200 mm SrTiO₃ Wafers
- Epitaxial SrTiO₃ on Si or SOI
- 5-500 nm thickness with or without 2 um SiO2 layer
- Single- or double-side polished
50 mm SrTiO₃ Wafers
- Epitaxial SrTiO₃ on Si or SOI
- 5-500 nm thickness with or without 2 um SiO2 layer
- 50 mm diameter
- Single- or double-side polished
Applications
La Luce Cristallina’s SrTiO₃ wafer platforms support research and device development across areas including:
- Quantum devices
- Cryogenic electronics
- Nonlinear devices
- Tunable dielectric devices
- Advanced semiconductor research
Technical Resources
Explore La Luce Cristallina’s research, technical publications, and news related to SrTiO₃, quantum paraelectric materials and advanced oxide-integrated devices.
La Luce Cristallina Launches CMOS-Compatible Oxide Pseudo-Substrate for Scalable Silicon Integration
This article highlights La Luce Cristallina’s CMOS-compatible oxide pseudo-substrate for growing high-quality epitaxial SrTiO₃ directly on 200 mm silicon and SOI wafers. The platform is designed to improve scalability, cost, yield, and compatibility with standard semiconductor tools, helping support the transition of oxide-based devices from laboratory research to manufacturable systems for quantum, RF, sensing, and advanced computing applications.
La Luce Cristallina Launches Quantum Paraelectric Strontium Titanate on Insulator Wafer Platform
This release introduces La Luce Cristallina’s silicon-based quantum paraelectric strontium titanate on insulator (QP-STOI) wafer platform for quantum, cryogenic, and nonlinear device applications. The platform combines a highly insulating STO layer with silicon-compatible manufacturing, enabling researchers to leverage STO’s voltage-tunable dielectric behavior at cryogenic temperatures for applications including qubit readout, tunable microwave components, sensing, and emerging electro-optic and electromechanical devices. The CMOS- and foundry-compatible platform is currently available in 2-inch wafers, with plans to scale to 200 mm.
Frequently Asked Questions
What is SrTiO₃ on silicon?
SrTiO₃ on silicon integrates crystalline strontium titanate (SrTiO₃/STO) with silicon substrates, providing a platform for incorporating the material’s functional properties into semiconductor-compatible devices.
Can SrTiO₃ be integrated with SOI?
Yes. La Luce Cristallina produces epitaxial SrTiO₃ on silicon-on-insulator (SOI), enabling researchers and device developers to integrate crystalline STO with semiconductor-compatible wafer platforms.
What is SrTiO₃ used for?
SrTiO₃ supports research and device development across quantum, cryogenic, nonlinear, tunable dielectric, RF, sensing, and other advanced semiconductor applications.
What SrTiO₃ wafer sizes and thicknesses are available?
La Luce Cristallina offers SrTiO₃ wafer platforms in multiple configurations, including 50 mm and 200 mm wafers. Available SrTiO₃ thicknesses range from 5 to 500 nm, with or without a 2 µm SiO₂ layer. Wafers are available in single- or double-side polished configurations.